FINALTERM EXAMINATION
Spring 2009
CS302- Digital Logic Design (Session - 2)
Question No: 1 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 2 ( Marks: 1 ) - Please choose one
Excess-8 code assigns _______ to “+7” ► 0000
► 1001
► 1000
► 1111
Question No: 3 ( Marks: 1 ) - Please choose one
NOR gate is formed by connecting _________ ► OR Gate and then NOT Gate
► NOT Gate and then OR Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma">
) and the carry (Cout) when A = 1 and B = 1? ► |
= 0, Cout = 0= 0, Cout = 0 ► = 0, Cout = 1
= 0, Cout = 1 ► = 1, Cout = 0
= 1, Cout = 0 ► = 1, Cout = 1
= 1, Cout = 1Question No: 5 ( Marks: 1 ) - Please choose one
A particular half-adder has ► 2 inputs and 1 output
► 2 inputs and 2 output
► 3 inputs and 1 output
► 3 inputs and 2 output
Question No: 6 ( Marks: 1 ) - Please choose one
The four outputs of two 4-input multiplexers, connected to form a 16-input multiplexer, are connected together through a 4-input __________ gate ► AND
► OR
► NAND
► XOR
Question No: 7 ( Marks: 1 ) - Please choose one
A Field-Programmable Logic Array can be programmed by the user and not by the manufacturer. ► True
► False
Question No: 8 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________ ► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators
► Bi-stable singlevibrators
Question No: 9 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________ ► Low-to-high transition of clock
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 10 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs. ► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 11 ( Marks: 1 ) - Please choose one
The glitches due to race condition can be avoided by using a ___________ ► Gated flip-flops
► Pulse triggered flip-flops
► Positive-Edge triggered flip-flops
► Negative-Edge triggered flip-flops
Question No: 12 ( Marks: 1 ) - Please choose one
The design and implementation of synchronous counters start from _________ ► Truth table
► k-map
► state table
► state diagram
Question No: 13 ( Marks: 1 ) - Please choose one
The hours counter is implemented using __________ ► Only a single Mod-12 counter is required
► Mod-10 and Mod-6 counters
► Mod-10 and Mod-2 counters
► a single decade counter and a flip-flop
Question No: 14 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find __________ ► The next state of a given present state
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the current state. ► Mealy machine
► Moore Machine
► State Reduction table
► State Assignment table
Question No: 16 ( Marks: 1 ) - Please choose one
A synchronous decade counter will have _______ flip-flops ► 3
► 4
► 7
► 10
Question No: 17 ( Marks: 1 ) - Please choose one
A multiplexer with a register circuit converts _________ ► Serial data to parallel
► Parallel data to serial
► Serial data to serial
► Parallel data to parallel
Question No: 18 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________ ► Parallel in / Serial out shift register
► Serial in / Parallel out shift register
► Parallel in / Parallel out shift register
► Serial in / Serial Out shift register
Question No: 19 ( Marks: 1 ) - Please choose one
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? ► 2
► 4
► 6
► 8
Question No: 20 ( Marks: 1 ) - Please choose one
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register. ► 1
► 2
► 4
► 8
Question No: 21 ( Marks: 1 ) - Please choose one
5-bit Johnson counter sequences through ____ states ► 7
► 10
► 32
► 25
Question No: 22 ( Marks: 1 ) - Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. ► Moore machine
► Meally machine
► Johnson counter
► Ring counter
Question No: 23 ( Marks: 1 ) - Please choose one
DRAM stands for __________ ► Dynamic RAM
► Data RAM
► Demoduler RAM
► None of given options
Question No: 24 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________ ► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 25 ( Marks: 1 ) - Please choose one
LUT is acronym for _________ ► Look Up Table
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 26 ( Marks: 1 ) - Please choose one
______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. ► Resolution
► Accuracy
► Quantization
► Missing Code
Question No: 27 ( Marks: 1 ) - Please choose one
In the circuit diagram of 3-bit synchronous countershown above, The red rectangle would be replaced which gate?
► AND
► OR
► NAND
► XNOR
Question No: 28 ( Marks: 1 ) - Please choose one
When both the inputs of edge-triggered J-K flop-flop are set to logic zero _________ ► The flop-flop is triggered
► Q=0 and Q’=1
► Q=1 and Q’=0
► The output of flip-flop remains unchanged
Question No: 29 ( Marks: 1 ) - Please choose one
A frequency counter ______________ ► Counts pulse width
► Counts no. of clock pulses in 1 second
► Counts high and low range of given clock pulse
► None of given options
Question No: 30 ( Marks: 1 ) - Please choose one
Stack is an acronym for _________ ► FIFO memory
► LIFO memory
► Flash Memory
► Bust Flash Memory
Question No: 31 ( Marks: 1 )
What is the role of MOS transistor in Mask ROM.Question No: 32 ( Marks: 1 )
The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. what will be the contents of register after two clock pulses the register contains?Question No: 33 ( Marks: 2 )
Draw the circuit diagram of gated S-R Latch.Question No: 34 ( Marks: 2 )
How many bytes will be there in 32 K x 4 memory?32 x 1024bytes x 4 = 131072 bytes
Question No: 35 ( Marks: 3 )
The ________ of first 74HC163 counter is connected to _______ and ________ inputs of other 74HC counter to form a single cascaded counterQuestion No: 36 ( Marks: 3 )
Given the following statement used in PLD programming:Y PIN 23 ISTYPE ‘com’;
Explain what does this statement mean?
Variable Y at output pin 23 which is a Combinational output available directly from the AND-OR gate array output.
Y = Variable Y
PIN 23 = pin number 23
ISTYPE “com” = output type Combinational
Question No: 37 ( Marks: 3 )
What is memory expansion process?Question No: 38 ( Marks: 5 )
Consider the table given below, apply the state reduction process on the states given in the table and reduce the number of states as much as possible.Present State | Next State | Output | ||
X=0 | X=1 | X=0 | X=1 | |
a | f | b | 0 | 0 |
b | b | c | 1 | 1 |
c | a | f | 0 | 1 |
d | e | d | 1 | 0 |
e | a | g | 0 | 1 |
f | d | e | 0 | 0 |
g | d | e | 0 | 0 |
Question No: 39 ( Marks: 5 )
Performance characteristics of D/A converters are determined by five parameters. Name them.Question No: 40 ( Marks: 10 )
Given below is the circuit diagram of bi-directional 4-bit serial in/serial out shift register. Register shifts data left or right depends on the 
signal applied. Explain how this circuit shifts data left and right. Question No: 41 ( Marks: 10 )
Briefly explain address multiplexing in DRAM.
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